This application claims the benefit of priority under 35 U.S.C. xc2xa7 119 to Japanese Patent Application Nos. 2001-41828, 2001-191781 and 2001-328204 filed on Feb. 19, 2001, Jun. 25, 2001 and Oct. 25, 2001, respectively, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device which dynamically stores data with a channel body as a storage node.
2. Description of the Related Art
A memory cell of a DRAM generally used as a large capacity RAM is composed of one MOS transistor and one capacitor, and electric charge is stored in the capacitor with using the MOS transistor as a selection switch. Data is read out at the sight of a change in the potential of a bit line by redistributing the electric charge stored in the cell capacitor to the electric charge of the bit line. Accordingly, there is a lower limit to the storage charge amount of the cell capacitor relative to the initial charge amount of the bit line.
In the DRAM, the parasitic capacity of the bit line reduces with scale-down, but since write charge to the cell also reduces with a reduction in power consumption and scale-down, the capacitance of the cell capacitor does not reduce. The capacitance of the capacitor is proportional to its area and the permittivity of a dielectric (a capacitor insulating film) and inversely proportional to the thickness of the capacitor insulating film. When the thickness of the capacitor insulating film is reduced, a tunnel current flows; hence, insulation properties cannot be maintained. For this reason, there is a limit of about 2 nm to the reduction in the thickness of a film, and a lot of time and money are required to look for and develop a dielectric film which has a permittivity higher than the permittivity of a silicon oxide film such as offsets an area reduced in proportion to the square thereof, is stable in terms of structure, fits a silicon CMOS process, and which is very reliable in actual use.
Therefore, from the mid-1980""s, a three-dimensional structure such as a stacked cell structure or a trench cell structure has been used for the capacitor of the DRAM. Even in these stacked cell structure and trench cell structure, recently the ratio of a plane size to a three-dimensional depth exceeds 10, resulting in a cigarette shape. Consequently, an etching limit to a silicon substrate in the case of a trench cell, and boring of a contact hole to bring a lower portion of a capacitor structure into contact with an upper portion thereof, filling of a conductor in this contact hole, and uniform covering properties of a dielectric in the case of a stacked cell come into question, and hence it has been said that those structures are unfit for further scale-down to a size under 100 nm.
An attempt to reduce the capacitor in size by using a gain of the MOS has been made from long ago, and this type of cell is called a gain cell. A drain current changes by the potential of a gate or a back gate of a read MOS transistor, and therefore the gain cell is classified broadly into two types, that is, one which uses a gate electrode as a storage node and the other which uses a channel body as a storage node. Examples of the one which uses the gate electrode of the read MOS transistor as the storage node are one composed of three transistors and one capacitor used in a 1 kbit DRAM by Intel Corporation in days of old and another composed of two transistors and one capacitor. As for capacitors, some are formed positively, and the others use a parasitic capacitor. In any case, in these gain cells, the number of devices is two or more, and gates (word lines) and drains (bit lines) are not common but separate for a write operation and a read operation, whereby the number of connections is large, and consequently, these gain cells are unfit for scale-down.
A gain cell of a type configured to use an SOI substrate, store charge with a channel body of a read MOS (sense MOS) as a storage node, and use a back gate bias effect is proposed. For example, the following documents are given.
(1) H. Wann and C. Hu, xe2x80x9cA Capacitorless DRAM Cell on SOI Substrate.xe2x80x9d IEDM Digest of Technical Papers, pp. 635-638, DEC., 1933
(2) M. R. Tack, et. al, xe2x80x9cThe Multistable Charge Controlled Memory Effect in SOI MOS Transistors at Low Temperatures,xe2x80x9d IEEE Transactions on Electron Devices, vol. no.5, pp. 1371-1382 May 1990.
In the document (1), one gate electrode is provided and hence this cell seemingly has a one transistor structure, but in reality a PMOS transistor region and an NMOS transistor region are provided under the gate, and its size is larger compared with a single one transistor structure. Moreover, it is necessary to write xe2x80x9c0xe2x80x9d before writing xe2x80x9c1xe2x80x9d. Also, as for write speed, it is more unfavorable compared with ordinary SRAM and DRAM. In Translated National Publication of Patent Application No. Hei 9-509284 by the same author, an operation example in which it is unnecessary to write xe2x80x9c0xe2x80x9d before writing xe2x80x9c1xe2x80x9d is disclosed, but the PMOS transistor region and the NMOS transistor region are similarly provided under the gate.
In the document (2), xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d cannot be simultaneously written in cells sharing a word line, and an erase operation by the use of an SOI substrate becomes necessary. As for write speed, this gain cell is more unfavorable compared with ordinary SRAM and DRAM.
Japanese Patent Laid-open No. Hei 3-171768 discloses a gain cell of a type configured to store charge with a channel body as a storage node and use a back gate bias effect. In this cell, the source/drain on the side where the bit line is not connected need to be isolated in a bit line direction or a word line direction, whereby the cell size is large. Moreover, it is necessary to write xe2x80x9c0xe2x80x9d before writing xe2x80x9c1xe2x80x9d, and thus regarding write speed, it is more unfavorable than ordinary SRAM and DRAM.
Japanese Patent Laid-open No. Hei 8-213624 discloses a gain cell of a type configured to store charge with a channel body as a storage node and use the fact that there is difference in parasitic bipolar collector current depending on the potential of the channel body. Also in this gain cell, it is necessary to write xe2x80x9c1xe2x80x9d before writing xe2x80x9c0xe2x80x9d, and regarding write speed, it is more unfavorable than ordinary SRAM and DRAM.
As described above, those recently proposed as a new DRAM need a special transistor structure and hence they have a complicated structure. Alternatively, even if they have a relatively simple structure, they have a drawback in controllability, whereby the achievement of high integration and high performance is difficult.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
a main gate provided between the source region and the drain region to form a channel in the channel body; and
an auxiliary gate provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate,
wherein the MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
According to another aspect of the present invention, a semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors having a first data state and a second data state, the semiconductor memory device, comprising:
a first semiconductor substrate;
auxiliary gates of the MIS transistors formed on the first semiconductor substrate to continue in one direction while their bottom faces and side faces are covered with an insulating film;
a second semiconductor substrate provided on the auxiliary gates with a first gate insulating film therebetween;
main gates of the MIS transistors formed on the second semiconductor substrate with a second gate insulating film to continue in parallel with the auxiliary gates;
source regions formed in space portions between the main gates and the auxiliary gates in the second semiconductor substrate;
drain regions formed apart from the source regions in space portions between the main gates and the auxiliary gates in the second semiconductor substrate;
source lines provided to be in contact with the source regions and continue in parallel with the main gates and the auxiliary gates;
an interlayer dielectric film covering the source lines; and
bit lines formed on the interlayer dielectric film in a direction intersecting the main gates and the auxiliary gates and being in contact with the drain regions.
According to a further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming an auxiliary gate on a first semiconductor substrate with a first gate insulating film therebetween;
forming an insulating film which is planarized after covering the auxiliary gate;
sticking a second semiconductor substrate on the insulating film;
polishing the first semiconductor substrate to form a semiconductor layer with a predetermined thickness;
forming a device isolation insulating film for device isolation in the first semiconductor substrate;
forming a main gate which faces the auxiliary gate on the semiconductor layer with the first gate insulating film therebetween; and
forming a source region and a drain region by ion-implanting impurities into the semiconductor layer with the main gate as a mask.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming a main gate on a first semiconductor substrate with a first gate insulating film therebetween;
forming a first insulating film which is planarized after covering the main gate;
sticking a second semiconductor substrate on the first insulating film;
polishing the first semiconductor substrate to form a semiconductor layer with a predetermined thickness;
forming a device isolation insulating film for device isolation in the first semiconductor substrate;
forming a second insulating film on the semiconductor layer;
boring an opening, which reaches the semiconductor layer, in the second insulating film to form a relay electrode connected to the semiconductor layer through the opening;
forming an auxiliary gate on the relay electrode with a second gate insulating film therebetween; and
forming a source region and a drain region by ion-implanting impurities into the semiconductor layer with the auxiliary gate as a mask.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming a first insulating film on a first semiconductor substrate;
boring an opening, which reaches the first semiconductor substrate, in the first insulating film to form a relay electrode connected to the first semiconductor substrate through the opening;
forming an auxiliary gate on the relay electrode with a first gate insulating film therebetween;
forming a second insulating film which is planarized after covering the auxiliary gate;
sticking a second semiconductor substrate on the second insulating film;
polishing the first semiconductor substrate to form a semiconductor layer with a predetermined thickness;
forming a device isolation insulating film for device isolation in the first semiconductor substrate;
forming a main gate on the semiconductor layer with a second gate insulating film therebetween; and
forming a source region and a drain region by ion-implanting impurities into the semiconductor layer with the main gate as a mask.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming a semiconductor layer on a semiconductor substrate with a first insulating film therebetween;
burying a device isolation insulating film in the semiconductor layer to demarcate device-formed regions device-isolated in a first direction;
burying a main gate, which faces a side face of the semiconductor layer with a first gate insulating film therebetween, in the device isolation insulating film;
forming an auxiliary gate, which faces the semiconductor layer with a second gate insulating film therebetween, on an upper face of the semiconductor layer in a state in which the auxiliary gate is electrically connected to the main gate and by using a material with a work function different from that of the main gate; and
forming a source region and a drain region by ion-implanting impurities into the semiconductor layer with the auxiliary gate as a mask.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor memory device, comprising:
forming a gate electrode material film on a first semiconductor substrate with a first insulating film therebetween;
bonding a second semiconductor substrate on the gate electrode material film with a first gate insulating film therebetween;
forming a device isolation insulating film in the second semiconductor substrate to demarcate device-formed regions continuing in a first direction in a stripe form;
depositing a second insulating film on the second semiconductor substrate where the device-formed regions are demarcated and pattern-forming the second insulating film as dummy gates continuing in a second direction orthogonal to the first direction;
etching the second semiconductor substrate, the first gate insulating film, and the gate electrode material film sequentially with the dummy gates as a mask to form auxiliary gates out of the gate electrode material film to continue in the second direction;
burying a third insulating film halfway in a thickness direction of the second semiconductor substrate in a space between the dummy gates;
forming a semiconductor layer on the third insulating film in the space between the dummy gates so that side faces thereof touch the second semiconductor substrate;
removing the dummy gates and forming a second gate insulating film on a surface of the exposed second semiconductor substrate;
burying main gates continuing in parallel with the auxiliary gates in space portions in the semiconductor layer;
ion-implanting impurities into the semiconductor layer to form source regions and drain regions;
forming source lines being in contact with the source regions and continuing in the second direction; and
forming an interlayer dielectric film covering the source lines and forming bit lines being in contact with the drain regions and continuing in the first direction on the interlayer dielectric film.